The present invention relates to semiconductor devices and more particularly to semiconductor chips used in a semiconductor device in which a plurality of semiconductor chips are stacked.
In the recent years, multilayer semiconductor devices have been proposed in which stacked semiconductor chips are placed in one package and the stacked semiconductor chips are coupled through through-silicon vias penetrating semiconductor substrates. An example of such a multilayer semiconductor device is disclosed in the publication of Japanese Patent No. 5654855.
The semiconductor device described in the publication of Japanese Patent No. 5654855 includes a plurality of memory chips which are stacked, in which each of the memory chips includes a plurality of memory banks, a plurality of read/write buses allocated to the memory banks respectively, and a plurality of through-silicon vias allocated to the read/write buses respectively, penetrating the memory chip. Regarding the through-silicon vias of the memory chips, several through-silicon vias located at the same position as seen in the stacking direction are commonly coupled among the memory chips and in response to a request for access, the memory chips each simultaneously activate memory banks located at different positions as seen in the stacking direction so that input and output of data are performed simultaneously through the through-silicon vias located at different positions as seen in the stacking direction.